1. Technical Field
The present subject matter relates to power management in a processor.
2. Background Information
Power efficiency is a significant requirement across a broad range of systems, ranging from small portable devices to rack-mounted server systems. Even in systems for which high performance is desired, power efficiency still may be a concern. Power efficiency is effected both by hardware design and component choice as well as software-based run-time power management techniques.
A complementary metal oxide semiconductor (“CMOS”) circuit experiences both “active” and “static” power consumption. Active power consumption occurs when the circuit is actively switching from one logic state to another. Active power consumption is caused both by “switching” current and “through” current (current that flows when both P and N-channel transistors are both on momentarily). Static power consumption results from reverse bias leakage and occurs even when the circuit is not actively switching. The total power consumption of a CMOS circuit is the sum of both active and static power consumption.
With conventional CMOS process technology, power savings may occur by simply gating off the clocks. In such circuits in this state, active power consumption falls to zero and the resulting leakage becomes relatively minimal. However, in more recently developed CMOS technology, the size of the transistors advantageously has been reduced, but with an undesirable increase in leakage current. As a result, some CMOS circuits experience undesirably high current draw even with all clocks gated off
Various hardware and software techniques have been employed to help manage the power state of a circuit or a complete system. While some of these techniques may be satisfactory, there still remains a need for improvement in the power management of individual semiconductor devices (e.g., processors), particularly for semiconductor devices having relatively high leakage currents when active power consumption is reduced.